Sunday, 11 January 2015

Functional Coverage

"A  user_defined metric that measures how much of the design specification has been exercised."
"Measures  whether scenarios, corner cases, invariants and other design conditions have been observed, validated and tested."
Functional Coverage Constructs

The SystemVerilog functional coverage constructs  enable:

  •  Coverage of variables and expressions, as well as cross coverage  between them.
  • Automatic as well as user-defined coverage bins.
  • Associate bins with sets of values, transitions, or cross products.
  • Filtering conditions at multiple levels.
  • Events and sequences to automatically trigger coverage  sampling.

Covergroup
covergroup is like a user defined type that encapsulated and specifies the coverage"

  • It can be defined in a package , module , program , interface or class
  • Once defined multiple instances can be created using new()
  • Parameters to new() enable customization of different instances
          – Ref argument enables different variables to be sampled by different instances of covergroup

Coverage points
  • A covergroup can contain one or more coverage points that  are  integral variables or integral expressions.
  • Coverage points imply a set of bins associated with its sampled  values or its value transitions.
  • The bins can be explicitly defined by the user or automatically created  by SystemVerilog.
  • Label is the name of the coverage point.
  • This name can be used to add this coverage point to a cross  coverage specification, or to access the methods of the coverage point.


Example 1: Define Covergroup, Coverpoint, Bins

bins fixed1 [] = {1:10;1,4,7}; // 13 bins are created
bins fixed2 [4] = {1:10;1,4,7}; // 4 bins are created
// with distribution <1,2,3>, <4,5,6>, <7,8,9>, <10,1,4,7>

bit [9:0] v_a;  // the maximum value is 1023
covergroup cg @(posedge clk);
      coverpoint v_a{
      bins a = {[0:63],65}; // single a bin collects v_a  // 65 b bins
      bins b[] = {[127:150],[148:191]} ; //overlapping values 
      bins c[] = {200,201,202}; // 3 c bins
      bins d = {[1000:$]}; // single d bin; $ is 1023
      bins others[] = default;} // everything else
endgroup

To conditionally disable sampling use the iff construct

covergroup g4;
    coverpoint s0 iff (!reset);
endgroup

Triggering a Cover Group

The major parts of the functional coverage is are the sampled data values and the time
when they are sampled.When new values are ready  your testbench triggers the cover group. This can be done using
  • Procedural sample () function
  • Blocking Expression
    •  wait or @ to block on signals or events
  • Triggering on a SystemVerilog Assertion
Example 2: Cover Group With an Event Trigger

class xyz;
  bit [3:0] m_x;
  int m_y;
  bit m_z;
  
 // This covergroup will be automatically sampled each time there is a change in value of m_z. 
 covergroup cov1 @m_z; 
     coverpoint m_x;
     coverpoint m_y;
  endgroup

  // This covergroup will be automatically sampled each time there is a posedge on "clk" signal. 
 covergroup cv1 @(posedge clk);
      coverpoint m_x; 
  endgroup

  function new()
    cov1 = new; 
    cv1 = new;
    cv2 = new; 
  endfunction

endclass

The advantage of using an event over calling the sample method directly is that you
may be able to use an existing event such as one triggered by an assertion, as shown Example 3 & 4

Example 3: Module with SystemVerilog Assertion

 module mem(simple_bus sb);
 bit [7:0] data, addr;
 event write_event;
    cover property 
    (@(posedge sb.clock) sb.write_ena==1)
    -> write_event;

endmodule

Example 4: Triggering a cover group with an SVA

program automatic test(simple_bus sb);
 covergroup Write_cg @($root.top.m1.write_event);
      coverpoint $root.top.m1.data;
      coverpoint $root.top.m1.addr;
 endgroup
Write_cg wcg;
initial begin
 wcg = new();
// Apply stimulus here
 sb.write_ena <= 1;
 ...
 #10000 $finish;
 end
endprogram